Switching apparatus

ABSTRACT

An apparatus for switching data between a first set of bitstreams and a second set of bitstreams, each of said bitstreams being divided into recurring frames and each of said recurring frames being divided into time slots, is disclosed. The switch comprises a first set of switching elements, at least one intermediate set of switching elements, and a last set of switching elements. Each switching element comprises a number of input ports and a number of output ports. The input ports of the first set of switching elements are arranged to receive the first set of bitstreams and the output ports of the last set of switching elements are arranged to provide said second set of bitstreams. Furthermore the switching elements are arranged so that there are more than one path from a switching element in the first stage to a switching element in the last stage. Each switching element is arranged so that it provides for both time and space switching of data from incoming bitstreams, referring to the input ports of the switching element, to outgoing bitstreams, referring to the output ports of the switching element.

FIELD OF THE INVENTION

[0001] The present invention generally relates to the field of data- andtelecommunications, and more specifically to multipath multistageswitches.

BACKGROUND OF THE INVENTION

[0002] When constructing large scale switches, it is often advantageousto use smaller building blocks in order to increase the scalability ofthe switch. One known building block with good scalability is multistageswitches. A multistage switch is in turn built up by smaller switchingelements, which are arranged in stages. Each switching element has anumber of input ports and a number of output ports. For some of thesemultistage switches, output ports of a switching element in one stageare connected to input ports of different switching elements in a nextstage. Thus, if there are at least three stages in such a multistageswitch, there is more than one path from an input port of a switchingelement in the first stage to an output port of a switching element inthe last stage. This type of multistage switches is referred to asmultipath multistage switches herein. By using the features of amultipath multistage switch, it is possible to create a so-callednon-blocking multistage switch.

[0003] Early prior art non-blocking multistage switches are built up ofan equal number of switching elements in each stage and connectionsbetween each switching element in one stage and each switching elementin a next stage. However, for these non-blocking multistage switchesthere are some limitations with respect to the channels that are to beswitched. For example, if so called multirate is introduced, i.e.different channels that are to be switched have different bandwidths,the non-blocking properties will not be preserved unless changes aremade to the structure of the switch and/or the way resources areallocated in the switch. The same goes for the introduction ofmulticast, where one channel should be switched from one input port tomore than one output port.

[0004] Prior art multipath multistage switches for switching timedivision multiplexed bitstreams are built up of time and space switchingelements in the first and the last stage and space switching elements inintermediate stages, i.e. stages in-between the first and the laststage. Thus, when establishing a channel between an input port and anoutput port in such a multipath multistage switch, there are twoconditions that need to be satisfied. First, the bandwidth must beavailable on all connections and in all switching elements on a pathbetween the input port and the output port. Second, since theintermediate switching elements only perform space switching, thebandwidth must be available in corresponding time slots of frames of bitstreams on all connections on the path between the input port and theoutput port. This limits the freedom of establishing channels throughthe switch and makes the control of the establishment of channelscomplex, especially in the case of multicast. In prior art multistageswitches the freedom is usually increased by introducing time expansionand/or an increase of the number of space switching elements inintermediate stages (see for example Soung C. Liew et al “Blocking andNonblocking Multirate Clos Switching Networks, IEEE/ACM Transactions onNetworking, Vol. 6, No. 3, June 1998). Time expansion means that thedata transfer rate is higher within the multipath multistage switch thanit is on input ports and output ports of the multipath multistageswitch. However, the introduction of time expansion and/or an increaseof the number of switching elements in intermediate stages will lead toan increased demand of accuracy in synchronisation or an increasedcomplexity of the multipath multistage switch, respectively. This willmake the switch costly. For a multirate switch the blocking might besevere due to the inability to fit in large channels when several linksare utilised. In the extreme case it can be shown that the timeexpansion or the number of intermediate stages required might go toinfinity if the channel can be of any size.

[0005] This problem of limited freedom of establishing channels throughthe switch and thus, the complex control of the establishment ofchannels in prior art multipath multistage switches, is, as mentionedabove, especially severe in the case of multicast. This is due to thefact that, in the case of multicast, it is preferable that the copyingof the data pertaining to a channel is made in as late a stage aspossible in order to save bandwidth in the earlier stages. In prior artmultipath multistage switches it is difficult to find one switchingelement in an intermediate stage that can carry the multicast channelfrom one input port to a number of output port since the data pertainingto the channel must be copied into corresponding time slots in frames ofoutgoing bitstreams at the output ports as they were received at theinput port.

[0006] Furthermore, the introduction of multirate networks gives rise toproblems with the allocation of resources to channels in multipathmultistage switches. For example, when resources are allocated tochannels these resources must be allocated so that fragmentation of theresources is avoided. Fragmentation may give rise to a situation where anew channel is to be established, for which the resources are availablein the switch, but since resources are fragmented, the resources are notavailable on one path through the switch. In some prior art switchesfragmentation is avoided by the application of methods for optimisingthe resource allocation of the channels (see for example Soung C. Liewet al “Blocking and Nonblocking Multirate Clos Switching Networks,IEEE/ACM Transactions on Networking, Vol. 6, No. 3, June 1998). However,even though the resource allocation is optimised when the channels areestablished, fragmentation may still arise. This is due to the factthat, over time, new channels will be established and old channels willbe terminated. In some prior art multipath multistage switches, this issolved by moving channels that are already established so that theresources are available on one path through the switch. The methods foroptimising the bandwidth allocation of the channels and the moving ofchannels that are already established, will require information of thestate of each switching element of the multipath multistage switch. Thecomplexity of moving channels grows with the switch since globalknowledge is required. Thus, a problem with these prior art multipathmultistage switches is that the complexity of the resource allocationwill be high. Another problem is that, even though the resourceallocation is optimised and already established channels are moved, thesituation described above, where a new channel cannot be establishedeven though the resources are available in the switch, may still occur.

[0007] Furthermore, in some prior art switches resource fragmentation isalleviated by the introduction of time expansion and/or an increase ofthe number of switching elements in intermediate stages. However, theintroduction of time expansion and/or an increase of the number ofswitching elements in intermediate stages will lead to an increaseddemand of accuracy in synchronisation or an increased complexity of themultipath multistage switch, respectively. Furthermore, for multicast ofmultirate channels, the introduction of time expansion and/or anincrease of the number of switching elements in intermediate stages theswitch will only decrease the level of blocking, i.e. the switch willnot be non-blocking.

SUMMARY OF THE INVENTION

[0008] One object of the invention is to eliminate the problem of severeblocking when establishing multirate channels in multipath multistageswitches. Thus, according to a first aspect of the invention, amultipath multistage switch which provides greater freedom as to thepossibilities of switching channels through the switch, is provided. Themultipath multistage switch according to the invention comprises anumber of switching elements that are arranged in stages. Each switchingelement has a number of input ports and a number of output ports. Eachswitching element is arranged so that it provides for both time andspace switching of data from an incoming bitstream, referring to aninput port, to outgoing bitstreams, referring to the output ports.Furthermore, the output ports of each switching element in one stage areconnected to the input ports of more than one switching element in anext stage. Finally, the multipath multistage switch according to theinvention also comprises a control unit for controlling the time andspace switching of the switching elements.

[0009] Thus, when a channel is to be established between an input portand an output port in a multipath multistage switch according to theinvention, it is only required to find a path between the input port andthe output port on which path enough bandwidth to carry the channel isavailable on all connections and in all switching elements on the path.In other words, the allocation of time slots in a bitstream on aconnection is independent of the allocation of time slots in bitstreamson other connections. This is due to the fact that the switchingelements in all stages of the multipath multistage switch according tothe invention can perform time switching in addition to space switching.

[0010] In order to save bandwidth in the early stages of a multipathmultistage switch and thus to simplify the set-up of channels whenmulticast of channels is performed, the copying of channels on multipleconnections is preferably performed in a switching element of a latestage of the switch. In view of this, the time switching properties ofthe multipath multistage switch according to the invention areespecially advantageous.

[0011] In the multipath multistage switch according to the first aspect,the switching elements need not be located in the same equipment or evenon the same premise, but may also be distributed. In the case of adistributed multipath multistage switch the switching elements arepreferably connected to each other with optical fibres.

[0012] Furthermore, a switching element of the multipath multistageswitch according to the first aspect may comprise a set ofinterconnected switching elements. For example, a switching element mayin fact itself be a multipath multistage switch.

[0013] A second object of the invention is to eliminate the problem ofsevere blocking when establishing multicast channels in multipathmultistage switches, without increasing the complexity of resourceallocation. Thus, according to a second aspect of the invention, amethod for allocating bandwidth to a multicast channel from one inputport to at least two output ports in a multipath multistage switchaccording the first aspect of the invention, is provided. According tothe method it is determined whether there is enough available bandwidthto carry the channel in the at least two output ports or not. If thereis, it is determined whether there is one switching element in the lastbut one stage of the multipath multistage switch for which there isenough available bandwidth to carry the channel from the input port viathe one switching element to the at least two output ports. If this isthe case, the multicast channel may be established via this oneswitching element, if not it is determined whether there are twoswitching elements in the last but one stage of the multipath multistageswitch for which there is enough available bandwidth to carry thechannel from the input port via the two switching elements to the atleast two output ports. The method is continued until a number ofswitching elements in the last but one stage of the multipath multistageswitch for which there is enough available bandwidth to carry thechannel from the input port via the switching elements to the at leasttwo output ports, is found, or until it has been determined that noteven the total number of intermediate switching elements in the last butone stage of the multipath multistage switch have enough availablebandwidth to carry the channel from the input port via the switchingelements to the at least two output ports.

[0014] The method makes use of the recognition that performing multicastin as late a stage as possible will save bandwidth in earlier stages ofthe switch. Furthermore, the method utilises the fact that the switchingelements of all stages of the multipath multistage switch can performtime switching in addition to space switching. More specifically, themethod reduces the two conditions when establishing a multicast channelin prior art switches, i.e. that the bandwidth must be available andthat it must be available in corresponding time slots of frames of bitstreams on all connections on a path between the input port and theoutput ports, to the condition that the bandwidth must be available onall connections on a path between the input port and the output ports.This reduction increases the possibility that the multicast may beperformed in a switching element in the last but one stage of theswitch, which in turn saves bandwidth in earlier stages. Thus, thethroughput of the switch may be kept high without the utilisation ofcomplex methods for allocating bandwidth to channels.

[0015] A third object of the invention is to eliminate the problem offragmentation of resources without an increase of the complexity of theswitch structure. Thus, according to a third aspect of the invention, amultipath multistage switch comprising a number of switching elementsthat are arranged in a first stage, at least one intermediate stage, anda last stage, is provided. Each switching element has a number of inputports and a number of output ports. Each switching element in the firststage and the last stage is arranged so that it provides for time andspace switching of data in an incoming bitstream referring to an inputport to outgoing bitstreams referring to the output ports. Eachswitching element in the at least one intermediate stage is arranged sothat it provides for at least space switching of data from an incomingbitstream, referring to an input port, to outgoing bitstreams, referringto the output ports. Furthermore, the output ports of each switchingelement in one stage are connected to the input ports of more than oneswitching element in a next stage. On a bit level, the bitstreamsbetween output ports of switching elements and input ports of otherswitching elements are asynchronous, whilst on a frame level they aresynchronous. This adds a flexibility on the bit level which isadvantageous in the time switching, whilst it at the same time ensuresthat data that are received in the same frame at the first stage willarrive in coincident frames at the last stage regardless of along whichpath they have been transported through the switch. Furthermore, theswitching elements are arranged so that there is no phase drift betweenstart of frame signals received at switching elements in the same stage,and so that data which are received between a pair of consecutive startof frame signals at input ports of different switching elements in astage, will be sent between a pair of consecutive start of frame signalsto input ports of switching elements in a next stage and will bereceived between a pair of consecutive start of frame signals at inputports of the switching elements in the next stage. The multipathmultistage switch according to the invention also comprises a controlunit for controlling the time and space switching of the switchingelements in the first stage and the last stage and the space switchingin the switching elements of the at least one intermediate stage.

[0016] Due to the fact that the output ports of each switching elementin one stage are connected to the input ports of more than one switchingelement in a next stage, there are multiple paths from an input port ofa switching element of the first stage to an output port of a switchingelement in the last stage. This, together with the way the switch issynchronised and the presence of the control unit, will make it possibleto switch different portions of a single channel via different pathsthrough the switch. More specifically, data which are received between apair of consecutive start of frame signals and pertaining to the samechannel, may be switched via different paths from an input port of aswitching element in the first stage to an output port of a switchingelement of the last stage. This is due to the fact that data which arereceived between a pair of consecutive start of frame signals at theinput port of the switching element in the first stage, will be receivedbetween a pair of consecutive start of frame signals at an input port ofthe switching element in the last stage regardless via which path theyare switched. The control unit then keeps track of the data pertainingto the same channel between a pair of consecutive start of frame signal,and controls the switching element in the last stage so that these dataare sent from the output port of the switching element in the last stagebetween a pair of consecutive start of frame signals.

[0017] Note that the switching elements of the multipath multistageswitch according to the third aspect need not be located in the sameequipment or even on the same premise, but may also be distributed. Inthe case of a distributed multipath multistage switch the switchingelements are connected to each other with optical fibres.

[0018] According the third aspect an apparatus for switching databetween a first set of bitstreams and a second set of bitstreams, eachof said bitstreams being divided into recurring frames and each of saidrecurring frames being divided into time slots, is provided. Theapparatus comprises:

[0019] a first set of switching elements, at least one intermediate setof switching elements, and a last set of switching elements, whereineach switching element comprises a number of input ports and a number ofoutput ports, and

[0020] a control unit for controlling allocation of bandwidth inoutgoing bitstreams, referring to the output ports of the switchingelements, said control unit being operatively connected to each of theswitching elements.

[0021] The input ports of said first set of switching elements arearranged to receive said first set of bitstreams and the output ports ofeach switching element in said first set of switching elements areoperatively connected to input ports of more than one switching elementin one of said at least one intermediate set of switching elements. Theinput ports of said last set of switching elements are operativelyconnected to output ports of more than one switching element in one ofsaid at least one intermediate set of switching elements and the outputports of said last set of switching elements are arranged to send saidsecond set of bitstreams. Said switching elements are arranged so thatdata which are received between a pair of consecutive start of framesignals at input ports of switching elements in said first set ofswitching elements, will be received between a pair of consecutive startof frame signals at input ports of switching elements in said last setof switching elements.

[0022] In one embodiment of the apparatus according to the third aspect,each one of said first set of switching elements and said last set ofswitching elements is arranged so that it provides for both time andspace switching of data from incoming bitstreams, referring to the inputports of the switching element, to outgoing bitstreams, referring to theoutput ports of the switching element, and each one of said at least oneintermediate set of switching elements is arranged so that it providesfor space switching of data from incoming bitstreams, referring to theinput ports of the switching element, to outgoing bitstreams, referringto the output ports of the switching element.

[0023] In another embodiment of the apparatus according to the thirdaspect, each switching element is arranged so that it provides for bothtime and space switching of data from incoming bitstreams, referring tothe input ports of the switching element, to outgoing bitstreams,referring to the output ports of the switching element.

[0024] In yet another embodiment of the apparatus according to the thirdaspect, said switching elements each comprise a slot mapping tabledesignating, for each outgoing time slot of frames of outgoingbitstreams, referring to the output ports of the switching element, anincoming time slot of a frame of an incoming bitstream, referring to aninput port of the switching element, from which incoming time slot datathat should be written into to the outging time slot should becollected, and said control unit is arranged to control the behaviour ofthe slot mapping table of each switching element.

[0025] Furthermore, a switching element of the multipath multistageswitch according to the third aspect may comprise a set ofinterconnected switching elements. For example, a switching element mayin fact itself be a multipath multistage switch.

[0026] Furthermore, according to a fourth aspect of the invention, amethod for switching multirate channels in a multipath multistageswitch, that eliminates the problem with fragmentation of resourceswithout an increase of the complexity of the switch structure, isprovided. The multistage switch comprises a number of switching elementsarranged in a first stage, at least one intermediate stage, and a laststage. Each switching element has a number of input ports and a numberof output ports. Furthermore, the output ports of each switching elementin one stage are connected to the input ports of more than one switchingelement in a next stage. The switching elements are arranged so thatdata, which are received between a pair of consecutive start of framesignals at input ports of switching elements in one stage, are sentbetween a pair of consecutive start of frame signals to input ports ofswitching elements in a next stage and received at the input ports ofthe switching elements in the next stage between a pair of consecutivestart of frame signals. Furthermore, consider a case where datapertaining to a single channel are received in different time slotsbetween a pair of consecutive start of frame signals at an input port ofa switching element of the first stage, and there is no single paththrough the switch having enough capacity for carrying the channelthrough the switch. Then, in accordance to the invention, the channeldata of different time slots are switched via different paths, i.e. viadifferent switching elements in the at least one intermediate stage, toan input port of a switching element of the last stage. Finally, saiddata pertaining to the single channel are mapped into different timeslots that are sent between a pair of consecutive start of frame signalsfrom the switching element of the last stage.

[0027] The method eliminates the problem with fragmentation of theresources in a multipath multistage switch when switching multiratechannels. This is done by switching different portions of a singlechannel via different paths through the switch, i.e. channel data ofdifferent time slots, but pertaining to the same channel, are switchedvia different paths. Thus, even though there is no single path throughthe switch that has enough available bandwidth to carry a channel, thechannel may still be switched through multipath multistage switch aslong as there are a set of paths that together have enough bandwidth tocarry the channel. Furthermore, the possibility of switching differentportions of a channel via different paths through the switch facilitatessimple, optimal resource allocation rules for establishing channelsthrough a multipath multistage switch.

[0028] According to the fourth aspect a method for switching datapertaining to a single channel via different paths through a switchingapparatus comprising a first set of switching elements, an intermediateset of switching elements, and a last set of switching elements, whereineach switching element comprises a number of input ports and a number ofoutput ports, and wherein the output ports of said first set ofswitching elements are operatively connected to the input ports of saidintermediate set of switching elements, and wherein the output ports ofsaid intermediate set of switching elements are operatively connected tothe input ports of said last set of switching elements, is provided. Themethod comprises the steps of:

[0029] receiving, at an input port of a switching element of said firstset of switching elements, data pertaining to a single channel in atleast two time slots, wherein said data are received between a pair ofconsecutive start of frame signals;

[0030] sending a first portion of said data in at least one time slotfrom a first output port of said switching element of said first set ofswitching elements to an input port of a first switching element of saidintermediate set of switching elements and sending a second portion ofsaid data in at least one time slot from a second output port of saidswitching element of said first set of switching elements to an inputport of a second switching element of said intermediate set of switchingelements, wherein said first portion of said data and said secondportion of said data are sent between a pair of consecutive start offrame signals;

[0031] receiving said first portion of said data at said input port ofsaid first switching element of said intermediate set of switchingelements and receiving said second portion of said data at said inputport of said second switching element of said intermediate set ofswitching elements, wherein said first portion of said data and saidsecond portion of said data are received between a pair of consecutivestart of frame signals;

[0032] sending said first portion of said data in at least one time slotfrom an output port of said first switching element of said intermediateset of switching elements to a first input port of a switching elementof said last set of switching elements and sending said second portionof said data in at least one time slot from an output port of saidsecond switching element of said intermediate set of switching elementsto a second input port of said switching element of said last set ofswitching elements, wherein said first portion of said data and saidsecond portion of said data are sent between a pair of consecutive startof frame signals;

[0033] receiving said first portion of said data at said first inputport of said switching element of said last set of switching elementsand receiving said second portion of said data at said second input portof said switching element of said last set of switching elements,wherein said first portion of said data and said second portion of saiddata are received between a pair of consecutive start of frame signals;

[0034] sending said first portion of said data in at least one time slotfrom an output port of said switching element of said last set ofswitching elements and sending said second portion of said data in atleast one time slot from said output port of said switching element ofsaid last set of switching elements, wherein said first portion of saiddata and said second portion of said data are sent between a pair ofconsecutive start of frame signals.

[0035] Furthermore, according to a fifth aspect of the invention, amethod for allocating bandwidth to a channel from an input port of aswitching element in a first stage to an output port of a switchingelement of a last stage of a multipath multistage switch, thateliminates the problem with fragmentation of resources without anincrease of the complexity of the switch structure, is provided.According to the method a number of paths from the input port to theoutput port, which paths together have enough available bandwidth tocarry the channel, are found. More specifically, for a multipathmultistage switch according to the third aspect of the invention whichhas a first stage, an intermediate stage and a last stage, the method isperformed as follows. First, a first path from the switching element ofthe first stage via one of the switching elements in the intermediatestage to the switching element in the last stage, is checked foravailable bandwidth. If the available bandwidth of the first path is notenough to carry the channel, a second path from the switching element ofthe first stage via another one of the switching elements in theintermediate to the switching element in the last stage, is checked foravailable bandwidth. This is continued until the joint bandwidth ofpaths from the switching element of the first stage via different onesof the switching elements in the intermediate to the switching elementin the last stage, is large enough to carry the channel.

[0036] The method utilises the fact that channel data of different timeslots, but pertaining to the same channel, may be switched via differentpaths in a multipath multistage switch according to the third aspect ofthe invention.

[0037] According to the fifth aspect of the invention a method forallocating, to a single channel, time slots in frames of bitstreams froma switching element in a first set of switching elements to twoswitching elements in an intermediate set of switching elements and inframes of bitstreams from said two switching elements in saidintermediate set of switching elements to a switching element in a laststage, is provided. The method comprises the steps of:

[0038] identifying a first switching element in the intermediate stage,for which there is at least one available time slot in each frame of abitstream from said switching element in the first set of switchingelements to said first switching element in said intermediate set ofswitching elements, and at least one available time slot in each frameof a bitstream from said first switching element in said intermediateset of switching elements to said switching element in said last set ofswitching elements;

[0039] allocating to said channel said at least one available time slotin the bitstream from said switching element in the first set ofswitching elements to said first switching element in said intermediateset of switching elements, and said at least one available time slot inthe bitstream from said first switching element in said intermediate setof switching elements to said switching element in said last set ofswitching elements;

[0040] identifying a second switching element in the intermediate stage,for which there is at least one available time slot in each frame of abitstream from said switching element in the first set of switchingelements to said second switching element in said intermediate set ofswitching elements, and at least one available time slot in each frameof a bitstream from said second switching element in said intermediateset of switching elements to said switching element in said last set ofswitching elements; and

[0041] allocating to said channel said at least one available time slotin the bitstream from said switching element in the first set ofswitching elements to said second switching element in said intermediateset of switching elements, and said at least one available time slot inthe bitstream from said second switching element in said intermediateset of switching elements to said switching element in said last set ofswitching elements.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Exemplifying embodiments of the invention will be described belowwith reference to the accompanying drawings, wherein:

[0043]FIG. 1 is a schematic diagram of an embodiment of a multipathmultistage switch according to the invention;

[0044]FIG. 2 shows an exemplifying embodiment of a switching element inthe multipath multistage according to FIG. 1;

[0045]FIG. 3 schematically shows an example of the switching of amulticast channel in the multipath multistage switch shown in FIG. 1;

[0046]FIG. 4 is a flow chart of an embodiment of a method for allocatingbandwidth to a multicast channel in the multipath multistage switchshown in FIG. 1;

[0047]FIG. 5A-D schematically show different stages of the allocation ofbandwidth to a multicast channel in the multipath multistage switchshown in FIG. 1;

[0048]FIG. 6 is a schematic diagram of another embodiment of a multipathmultistage switch according to the invention;

[0049]FIG. 7 schematically shows an example of the switching differentportions of a single channel via multiple paths in the multipathmultistage switch shown in FIG. 4;

[0050]FIG. 8 and schematically shows an example of the switching ofdifferent portions of a single channel via multiple paths in a multipathmultistage switch which is a combination of the multipath multistageswitches shown in FIG. 1 and FIG. 5;

[0051]FIG. 9 is a flow chart of an embodiment of a method for allocatingbandwidth to different portions of a single channel on multiple paths ina multipath multistage switch which is a combination of the multipathswitches shown in FIG. 1 and FIG. 6;

[0052]FIG. 10A-D schematically show different stages of the allocationof bandwidth to different portions of a single channel on multiple pathsin the multipath multistage switch shown in FIG. 8;

[0053]FIG. 11 schematically shows an alternative realisation of amultipath multistage switch according to FIG. 1 or FIG. 6;

[0054]FIG. 12 schematically shows a network in which the multipathmultistage switch in FIG. 1 or FIG. 6, respectively, may be used withadvantage; and

[0055]FIG. 13 schematically shows a scenario where the multipathmultistage switch in FIG. 1 or FIG. 6, respectively, is applied in an IPnetwork.

DETAILED DESCRIPTION OF EMBODIMENTS

[0056] In FIG. 1, a schematic diagram of one embodiment of a multipathmultistage switch according the invention, is shown. The multipathswitch comprises nine switching elements arranged in a first stage 105,an intermediate stage 110 and a last stage 115, each stage having threeswitching elements. Each switching element has three input ports andthree output ports, where the output ports of a switching element in onestage are connected input ports of different switching element in a nextstage. In operation, the input ports of the switching elements will beconnected to receive data in bitstreams which are divided intoessentially fixed sized frames, which in turn are divided into fixedsized time slots. Each of the switching elements is then capable ofperforming switching in both space and time of data from an incomingbitstream, referring to an input port of the switching element, tooutgoing bitstreams, referring to the output ports of the switchingelement. In other words, data in a time slot of a frame in an incomingbitstream, referring to an input port of a switching element, may bemapped into an arbitrary time slot of a frame in an outgoing bitstream,referring to any one of the output ports of the switching element.Finally, the multipath multistage switch according to the invention alsocomprises a control unit 120 which is operatively connected to each ofthe switching elements and controls the time and space switching of theswitching elements. Note that the number of switching elements, thenumber of stages and the number of input and output ports of eachswitching element in FIG. 1 have been chosen merely as an example. Thenumbers may be chosen arbitrarily as long as the number of stages are atleast three and there are more than one path from an input port of aswitching element in the first stage 105 to an output port of aswitching element of the last stage 115. Moreover, the number ofswitching elements in the different stages need not be equal.

[0057] By using the multipath multistage switch shown in FIG. 1, thepossibility to find a path from a switching element in the first stage105 to a switching element in the last stage 115, which path can carry achannel is increased in comparison with prior art switches, since theswitching elements in the intermediate stage 110 also provide for timeswitching, i.e. data that are mapped into time slots of a frame in aincoming bitstream to a switching element in the intermediate stage 110may be mapped into arbitrary time slots of frames in outgoing bitstreamsfrom the switching element. In this case it is sufficient to find aswitching element in the intermediate stage 110 that has enoughavailable time slots in frames of an incoming bitstream from theswitching element in the first stage 105 to carry the channel and enoughavailable time slots in frames of an outgoing bitstream to the switchingelement in the last stage 115 to carry the channel.

[0058] An exemplifying embodiment of a switching element in themultipath multistage according to FIG. 1 will now be described withreference to FIG. 2. In FIG. 2, the switching element SW, which may bethe used in the multipath multistage switch shown in FIG. 1, receivestime slot data from three input bitstreams 1-3 and transmits thereceived time slot data to three output bitstreams 4-6. Accordingly, theswitch SW comprises three input medium access units 21-23 and threeoutput medium access units 65-68 providing access to the respectivebitstreams.

[0059] Each input medium access unit 21-23 is arranged to write eachframe received from the respective bitstream into a respective framebuffer 31-33. Each frame buffer 31-33 has capacity to store threesequential frames of the respective bitstream in three correspondingmemory areas or columns, 31 a-31 c, 32 a-32 c, and 33 a-33 c, alsocalled pages, each memory area having capacity to store one frame. Forexample, the frame buffer 31, which temporarily stores each framereceived from the bitstream 1 via the input medium access unit 21, willsequentially store a first frame in the memory page 31 a, the next(second) frame in the memory page 31 b, and the following (third) framein the memory page 31 c. Then, the following (fourth) frame will bestored again using the memory page 31 a, thus overwriting the previouslystored first frame. Also, note that the time slot data from the timeslots of a frame are written sequentially into corresponding time slotdata fields of the respective memory page, i.e. one data field for eachinput time slot.

[0060] At the same time, four time slot data selection units 45-47,which, may be provided, e.g., in the form of multiplexors or a tri-statebuses, are arranged to select time slot data to be transmitted into therespective output bitstreams 4-6 by deciding, for each output time slotto be transmitted into the respective output bitstreams, which framebuffer, and memory page thereof, and from which time slot data entrythereof (i.e. among the presently stored time slot data from all threeinput bitstreams 1-3) the time slot data slot is to be collected, orpassed on, to the respective output bitstream. Hence, each selectionunit 45-47 is connected to all three frame buffers 31-33 for theselection and collection of time slot data therefrom.

[0061] In order to know which frame buffer, page and entry or fieldthereof to be used for a specific output time slot, each selection unit45-47 has access to a respective slot mapping table 55-57, which, foreach time slot of the respective output bitstream frame and at arespective entry, provides one field (of a memory area or column 55 a-57a) designating the frame buffer and one field (of a memory area orcolumn 55 b-57 b) designating the entry or field thereof to be used forcollecting the given output time slot. The output time slot entries ofthe slot mapping tables 55-57 is preferably stored in the timesequential order of the corresponding output frame, and each slotmapping table is stepped through once each frame of the respectivebitstream.

[0062] Hence, when collecting time slot data for the first time slot ineach frame of the bitstream 4, the selection unit 45 will access thefirst entry of the slot mapping table 55, more specifically the firstdata field of the column 55 a and the first data field of the column 55b to derive information as to which one of the three frame buffers andwhich entry or field thereof that time slot data is to be collected forthe first output time slot of the frame of the bitstream 4. Also, theselection unit 45 will control the selection of which memory area orpage of each frame buffer 31-33 that is to be used for the collection oftime slot data for the frame currently being written into the bitstream4. Accordingly, the selection unit will pick time slot data in givenoutput order for each time slot of the output bitstream to receive timeslot data. Of course, the switch SW will only transmit time slot datainto those slots of the output bitstream allocated for that purpose.

[0063] For a more detailed description of the switching elementsreference is made to the International patent application WO99/25099,the complete disclosure of which is incorporated herein by reference.

[0064] In an embodiment of a multipath multistage switch according toFIG. 1 where each switching element is a switching element according toFIG. 2, the control unit would control the time and space switching ofeach switching element by means of the configuration and reconfigurationof the slot mapping table (SMT) of each switching element.

[0065]FIG. 3 schematically shows an example of the switching of amulticast channel from an input port of a switching element in the firststage 105 to output ports of the three switching elements in the laststage 110 in the multipath multistage switch shown in FIG. 1. In thefollowing, the switching elements of each stage of the multipathmultistage switch in FIG. 3 are referred to as a first, a second and athird switching element from top to bottom, the input ports of eachswitching element are referred to as a first, a second and a third inputport from top to bottom, and the output ports of each switching elementare referred to as a first, a second and a third output port from top tobottom. Data A, B and C pertaining to the multicast channel, arereceived in a first, a third and a fourth time slot, respectively, of aframe in an incoming bitstream at the first input port of the secondswitching element in the first stage. In the second switching element inthe first stage, the data A, B and C are mapped into a first, a secondand a fourth time slot, respectively, of a frame in an outgoingbitstream from the second output port of the second switching element inthe first stage, and sent to the second input port of the secondswitching element in the intermediate stage. In the second switchingelement of the intermediate stage, the data A, B and C are copied andmapped into time slots of frames in outgoing bitstreams from the first,the second and the third output ports of the second switching element ofthe intermediate stage. More specifically, the data A, B and C aremapped into a first, a second and a fourth time slot, respectively, of aframe in an outgoing bitstream from the first output port of the secondswitching element in the intermediate stage, the data A, B and C aremapped into a second, a third and a fourth time slot, respectively, of aframe in an outgoing bitstream from the second output port of the secondswitching element in the intermediate stage, and the data A, B and C aremapped into a first, a second and a third time slot, respectively, of aframe in an outgoing bitstream from the third output port of theswitching element in the intermediate stage. The frame in the outgoingbitstream from the first output port, the frame in the outgoingbitstream from the second output port, and the frame in the outgoingbitstream from the third output port of the second switching element inthe intermediate stage, are then sent to the second input port of thefirst switching element, the second input port of the second switchingelement, and the second input port of the third switching element in thelast stage, respectively. Finally, in the first switching element of thelast stage, the data A, B and C are mapped into a first, a third and afourth time slot, respectively, of a frame in an outgoing bitstream atthe first output port of the switching element. In the second switchingelement of the last stage, the data A, B and C are mapped into a second,a third and a fourth time slot, respectively, of a frame in an outgoingbitstream at the second output port of the switching element. In thethird switching element of the last stage, the data A, B and C aremapped into a first, a second and a fourth time slot, respectively, of aframe in an outgoing bitstream at the first output port of the switchingelement.

[0066] Note that in the switching element in the intermediate stage, thedata A, B and C are copied and mapped into different time slots of theframes in the outgoing bitstreams from the first output port, the secondoutput port and the third output port. This is possible since theswitching elements in the intermediate stage can perform time switchingin addition to space switching. Thus, the time slots in which datapertaining to the channel are mapped in the outgoing bitstream at one ofthe output ports of the switching element in the intermediate stage areindependent from the time slots in which data pertaining to the channelare mapped in the outgoing bitstreams at the other output ports of theswitching element. Moreover, the time slots in which data pertaining tothe channel are mapped in the outgoing bitstreams at the output ports ofthe switching element in the intermediate stage are independent from thetime slots in which data pertaining to the channel are mapped in theincoming bitstreams at the input port of the switching element.

[0067] Furthermore, the number of time slots in each frame is notessential to the invention. Thus, the fact that the number of time slotsin each frame is four in FIG. 2 is just an example.

[0068] The features of the multipath multistage switch in FIG. 1 areespecially advantageous in the case of multicast of channels, i.e. datapertaining to a channel should be switched from an input port of aswitching element in the first stage of a multipath multistage switch tooutput ports of at least two switching elements in the last stage. Forexample, consider a case where data pertaining to a channel are sent toone switching element in the intermediate stage where they are receivedin time slots of a frame in an incoming bitstream at an input port. Thedata are then to be copied into time slots of frames in outgoingbitstreams at more than one output port of the switching element of theintermediate stage and sent to the at least two switching elements inthe last stage. In this case, in the multipath multistage switchaccording to the invention, it is sufficient to find a switching elementin the intermediate stage that has enough available time slots in framesof an incoming bitstream from the switching element in the first stageto carry the channel, and enough available time slots in frames of anoutgoing bitstreams to the at least two switching elements in the laststage to carry the channel.

[0069]FIG. 4 shows a flowchart of an embodiment of a method forallocating bandwidth to a multicast channel with a bandwidth BW, whichmulticast channel is to be established from an input port of a switchingelement in a first stage to at least two output ports of switchingelements in a last stage of a multipath multistage switch as describedwith reference to FIG. 1. The input to the method when it is started instep 400, is the current bandwidth allocation in the multipathmultistage switch, and the input port and the at least two output portsof the multicast channel. First, in step 405, it is checked if there isat least BW available bandwidth in the outgoing bitstream from each ofthe at least two output ports of the multicast channel. If there is not,the multicast channel cannot be established and the method is ended instep 410. If there is at least BW available bandwidth, the desirednumber of switching elements j in the intermediate stage that themulticast channel should be switched through, is set to one in step 415.Then, it is checked, in step 420, if j is less than or equal to thenumber of switching elements in the intermediate stage. If j is not lessthan or equal to the number of switching elements in the intermediatestage the multicast channel cannot be established and the method isended in step 410. If j is less than or equal to the number of switchingelements in the intermediate stage, it is checked, in step 425, if thereis a set of j switching elements in the intermediate stage from whichthere is at least BW available bandwidth to each of the switchingelements where the at least two output ports of the multicast channelare located. If there is not a set of j such switching elements, j isincreased with one, in step 430, and the method is continued in step 420for this increased j. If there is a set of j such switching elements, itis checked, in step 435, if there is at least BW available bandwidthfrom the switching element in the first stage where the input port ofthe multicast channel is located to each of the set of j switchingelements. If there is not at least BW available bandwidth, the method iscontinued in step 425 where it is checked if there is another set of jswitching elements in the intermediate stage from which there is atleast BW available bandwidth to each of the switching elements where theat least two output ports of the multicast channel are located. If thereis at least BW available bandwidth from the switching element in thefirst stage where the input port of the multicast channel is located toeach of the set of j switching elements, the bandwidth BW is allocated,in step 440, to the multicast channel from the input port of themulticast channel to the j switching elements in the intermediate stage,and from the j switching elements in the intermediate stage to the atleast two output ports of the multicast channel. After step 440, themethod is continued in step 445 in which the switching element where theinput port of the multicast channel is located, each of the set of jswitching elements, and the switching elements where the at least twooutput ports of the multicast channel are located, are configured to mapdata pertaining to the multicast channel into the available time slots.Finally, the method is ended in step 450.

[0070] To illustrate the method described with reference to FIG. 4, anexample of the allocation of bandwidth to a multcast channel by means ofthe control unit 120 will be described in the following with referenceto FIG. 5A-D. FIG. 5A-D schematically show different stages of theallocation of bandwidth to a multicast channel in the multipathmultistage switch in FIG. 1. The allocation is done in accordance withthe method described with reference to FIG. 4. The same numbering of theswitching elements and their respective input ports and output ports asin the description above with reference to FIG. 3, will be used.Furthermore, only the connections of interest are indicated in the FIGS.5A-D. For these connection, an indication of occupied time slots offrames in bitstreams on each connection of interest are indicated as anO in the corresponding time slot.

[0071] The establishment of a channel with a bandwidth corresponding tothree time slots out of four in each frame, from the second input portof the third switching element of the first stage to the second outputport of the first switching element in the last stage and the thirdoutput port of the third switching element in the last stage, isrequested. The request is signalled to the control unit 120, which has afull view of the number of available time slots throughout the multipathmultistage switch. First, it is determined by means of the control unit120 if there is sufficient bandwidth in the two output ports to whichthe channel should be multicasted. Since the bandwidth requirement isbandwidth corresponding to three time slots in each frame and there isonly one out of four time slots that is occupied in each frame in theoutgoing bitstreams from the two output ports to which the channelshould be multicasted (see FIG. 5A), the bandwidth is sufficient. Next,the number of switching elements in the intermediate stage via which themulticast channel should be established is set to one and the availablebandwidth from each switching element in the intermediate stage to thefirst and the third switching element, respectively, is determined untilone switching element in the intermediate stage for which the bandwidthto the first and the third switching element, is sufficient to carry themulticast channel. The determination is done using a control unit 120which has a full view of the number of available time slots throughoutthe multipath multistage switch.

[0072] In FIG. 5A it is shown that the available time slots of eachframe in the outgoing bitstream from the first switching element in theintermediate stage to the first switching element in the last stage areonly two. Thus, the multicast channel cannot be established only throughthe first switching element in the intermediate stage.

[0073] In FIG. 5B it is shown that the available time slots of eachframe in the outgoing bitstream from the second switching element in theintermediate stage to the first switching element and the thirdswitching element in the last stage, respectively, are three. Thus, theavailable bandwidth is sufficient to carry the multicast channel.

[0074] Then, it is determined, using the control unit 120, whether thebandwidth from the third switching element in the first stage to thesecond switching element in the intermediate stage is sufficient tocarry the multicast channel. In FIG. 5B it is shown that there are twoavailable time slots of each frame in the outgoing bitstream from thethird switching element in the first stage to the second switchingelement in the intermediate stage. Thus, the multicast channel cannot beestablished only through the second switching element in theintermediate stage.

[0075] In FIG. 5C it is shown that the available time slots of eachframe in the outgoing bitstream from the third switching element in theintermediate stage to the first switching element and the thirdswitching element in the last stage, respectively, are three. Thus, theavailable bandwidth is sufficient to carry the multicast channel.Furthermore, it is shown that there are three available time slots ofeach frame in the outgoing bitstream from the third switching element inthe first stage to the third switching element in the intermediatestage. Thus, the multicast channel can be established through the thirdswitching element in the intermediate stage.

[0076] Having found one switching element in the intermediate stage thathas enough bandwidth to carry the channel, each switching elementthrough which the multicast channel is switched is configured so thatdata pertaining to the multicast channel are mapped into the availabletime slots in each of these switching elements. More specifically, theslot mapping table (SMT) of each of these switching elements isreconfigured using the control unit 120 which has a full view of theseSMT:s and thus, of which time slots are available. The reconfigurationis done first in switching elements in the last stage, then in switchingelements in the intermediate switch, and finally in switching elementsin the first stage.

[0077] In FIG. 5D, the mapping of data D, E and F pertaining to themulticast channel into the available time slots, is shown.

[0078] Referring now to FIG. 6, a schematic diagram of anotherembodiment of a multipath multistage switch according to the inventionis shown. The multipath switch comprises nine switching elementsarranged in a first stage, an intermediate stage and a last stage, eachstage having three switching elements. Each switching element has threeinput ports and three output ports, where the output ports of aswitching element in one stage are connected input ports of differentswitching element in a next stage. In operation, the input ports of theswitching elements will be connected to receive data in bitstreams whichare divided into essentially fixed sized frames, which in turn aredivided into fixed sized time slots. Each of the switching elements inthe first stage and the last stage is then capable of performingswitching in both space and time of data from an incoming bitstream,referring to an input port of the switching element, to outgoingbitstreams, referring to the output ports of the switching element. Inother words, data in a time slot of a frame in a bitstream, referring toan input port of a switching element in the first stage or the laststage, may be mapped into a arbitrary time slot of a frame in abitstream, referring to any of the output ports of the switchingelement. Each of the switching elements in the intermediate stage iscapable of performing space switching of data from an incomingbitstream, referring to an input port of the switching element, tooutgoing bitstreams, referring to the output ports of the switchingelement. In other words, data in a time slot of a frame in a bitstream,referring to an input port of a switching element in the intermediatestage, may be mapped into a corresponding time slot of a frame in abitstream, referring to any of the output ports of the switchingelement.

[0079] Note that the number of switching elements, the number of stagesand the number of input and output ports of each switching element havebeen chosen merely as an example. The numbers may be chosen arbitrarilyas long as the number of stages are at least three and there are morethan one path from an input port of a switching element in the firststage to an output port of a switching element of the last stage.Moreover, the number of switching elements in the different stages neednot be equal.

[0080] The multipath multistage switch is arranged so that there is nophase drift between the synchronisation signals of switching elements inthe same stage. In this embodiment this is achieved as follows. Aninternal selecting unit (not shown) in each of the switching elements inthe first stage selects a synchronisation signal from one of the inputports of the switching element. The selected synchronisation signalsfrom the switching elements in the first stage are then fed to anexternal selecting unit 605 that selects one of them and feeds it to theuppermost switching element in the intermediate stage. The uppermostswitching element then distributes the synchronisation signal to theuppermost switching element of the first and the last stages. Thesynchronisation signal is then fed downwards to each switching elementin each stage. Note that there are no constraints on the phases ofswitching element in different stages.

[0081] Furthermore, the multipath multistage switch is arranged so thatdata, which are received between a pair of consecutive start of framesignals at input ports of different switching elements in a stage, willbe sent between a pair of consecutive start of frame signals to inputports of switching elements in a next stage and will be received betweena pair of consecutive start of frame signals at input ports of theswitching elements in the next stage. In this embodiment this isachieved by using the distribution of the synchronisation signal asdescribed above and adapting the delay of connections between switchingelements in different stages.

[0082] Finally, the multipath multistage switch in FIG. 6 also comprisesa control unit (not shown) for controlling the time and space switchingof the switching elements in the first stage and the last stage and thespace switching in the switching elements of the at least oneintermediate stage. The control unit is operatively connected to each ofthe switching elements.

[0083]FIG. 7 schematically shows an example of the switching of a singlechannel via multiple paths from an input port of a switching element inthe first stage to an output port of a switching element in the laststage in the multipath multistage switch shown in FIG. 6. In thefollowing, the switching elements of each stage of the multipathmultistage switch in FIG. 7 are referred to as a first, a second and athird switching element from top to bottom, the input ports of eachswitching element are referred to as a first, a second and a third inputport from top to bottom, and the output ports of each switching elementare referred to as a first, a second and a third output port from top tobottom. Data G, H and I pertaining to the channel, are received in afirst, a third and a fourth time slot, respectively, of a frame in anincoming bitstream at the first input port of the first switchingelement in the first stage. Thus, the data G, H and I are receivedbetween a pair of consecutive start of frame signals. In the firstswitching element in the first stage, the data H and I are mapped into athird and a fourth time slot, respectively, of a frame in an outgoingbitstream at the first output port of the switching element in the firststage and sent to the first input port of the first switching element inthe intermediate stage. The data G are mapped into a second time slot ofa frame in an outgoing bitstream at the third output port of the firstswitching element in the first stage and sent to the first input port ofthe third switching element in the intermediate stage. In the firstswitching element of the intermediate stage, the data H and I, which arereceived in the third and the fourth time slot, respectively, of a frameat the first input port, are mapped into corresponding time slots, i.e.a third and a fourth time slot, respectively, of a frame in an outgoingbitstream at the first output port of the first switching element in theintermediate stage, and sent to the first input port of the firstswitching element in the last stage. Furthermore, in the third switchingelement of the intermediate stage, the data G, which are received in thesecond time slot of a frame at the first input port, are mapped into acorresponding time slot, i.e. a second time slot, of a frame in anoutgoing bitstream at the first output port of the third switchingelement in the intermediate stage, and sent to the third input port ofthe first switching element in the last stage. Since the data G, H and Iwere received in the first switching element in the first stage betweena pair of consecutive start of frame signals, the synchronisationfeatures of the multipath multistage switch described above, will ensurethat the data G, H and I will be sent from the first switching elementin the first stage between a pair of consecutive start of frame signals,and that they will be received in the respective switching elements inthe intermediate stage between a pair of consecutive start of framesignals. Furthermore, the data G, H and I will be sent from theswitching elements in the intermediate stage between a pair ofconsecutive start of frame signals, and they will be received in thefirst switching element in the last stage between a pair of consecutivestart of frame signals. Thus, it is possible, in the first switchingelement of the last stage, to map the data G, H and I into a first, asecond and a third time slot, respectively, of a frame in an outgoingbitstream from the first output port of the switching element.

[0084] Thus, it is understood that the way that a channel may be dividedinto portions that are switched via different paths through themultipath multistage switch in FIG. 6, will eliminate the problem withfragmentation in the case of multirate channels. Even though there is nosingle path through the multipath multistage switch in FIG. 6 that hasenough available bandwidth to carry a channel, the channel may still beswitched through multipath multistage switch as long as there are a setof paths that together have enough bandwidth to carry the channel.

[0085] The embodiments of a multipath multistage switch described withreference to FIG. 1 and FIG. 6, respectively, may be combined withadvantage. More specifically, an advantageous combination is a multipathmultistage switch having the synchronisation features of the multipathmultistage described with reference to FIG. 6, and the additionalfeature that the switching elements in the intermediate stage arecapable of performing time switching, in addition to space switching, ofdata from an incoming bitstream, referring to an input port of theswitching element, to outgoing bitstreams, referring to the output portsof the switching element, as is the case for the multipath multistageswitch described with reference to FIG. 1. FIG. 8 schematically shows anexample of the switching of a single channel via multiple paths from aninput port of a switching element in the first stage to an output portof a switching element in the last stage in such a combination themultipath multistage switch. As in the description with reference toFIG. 7, the switching elements of each stage of the multipath multistageswitch in FIG. 8 are referred to as a first, a second and a thirdswitching element from top to bottom, the input ports of each switchingelement are referred to as a first, a second and a third input port fromtop to bottom, and the output ports of each switching element arereferred to as a first, a second and a third output port from top tobottom. The main difference between these examples and the exampledescribed with reference to FIG. 7, is that the switching elements inthe intermediate stage are capable of performing time switching. Thus,data that are received in time slots of a frame in an incoming bitstreamat an input port of a switching element in the intermediate stage may bemapped into arbitrary time slots of a frame in an outgoing bitstream atany one of the output ports of the switching element in the intermediatestage. For example, in FIG. 8, data J that are received in a third timeslot of a frame in an incoming bitstream at the first input port of thethird switching element in the intermediate stage, are mapped into afourth time slot of a frame in an outgoing bitstream at the first outputport of the third switching element in the intermediate stage. Moreover,data that are received in time slots of a frame in an incoming bitstreamat an input port of a switching element in the first stage may even bemapped into time slots of frames in outgoing bitstreams at output portsof the switching element in the first stage in another order than theorder in the incoming bitstream. For example, in FIG. 8, data J and Kthat are received in a first and a third time slot, respectively, of aframe in an incoming bitstream at the first input port of the firstswitching element in the first stage, are mapped into a third time slotof a frame in an outgoing bitstream at the third output port of theswitching element and a first time slot of a frame in an outgoingbitstream at the first output port of the switching element in theintermediate stage, respectively. However, when the data J and Keventually are mapped into a frame in an outgoing bitstream at the firstoutput port of the first switching element in the last stage the orderof the data are the same as they were received at the first input portof the first switching element in the first stage.

[0086] Since the data J and K were received in the first switchingelement in the first stage in the same frame, i.e. between a pair ofconsecutive start of frame signals, the synchronisation features of themultipath multistage switch described above with reference to FIG. 6,will ensure that the data J and K will be sent from the first switchingelement in the first stage between a pair of consecutive start of framesignals, and that they will be received in the respective switchingelements in the intermediate stage between a pair of consecutive startof frame signals. Furthermore, the data J and K will be sent from theswitching elements in the intermediate stage between a pair ofconsecutive start of frame signals, and they will be received in thefirst switching element in the last stage between a pair of consecutivestart of frame signals. Thus, it is possible, in the first switchingelement of the last stage, to map the data J and K into a first and asecond time slot, respectively, of the same frame in an outgoingbitstream from the first output port of the switching element.

[0087]FIG. 9 shows a flowchart of an embodiment of a method forallocating bandwidth on multiple paths to a single channel with abandwidth BW, which channel is to be established from an input port of aswitching element in a first stage to an output port of a switchingelement in a last stage of a multipath multistage switch as describedwith reference to FIG. 8. The input to the method when it is started instep 900, is the current bandwidth allocation in the multipathmultistage switch, and the input port and the output port of thechannel. Furthermore, the switching elements of the intermediate stageare numbered consecutively, e.g. from top to bottom. First, in step 905,it is checked if there is enough available bandwidth in the output portof the channel to carry the channel. If there is not, the channel cannotbe established and the method is ended in step 910. If there is enoughavailable bandwidth in the output port of the channel, i, which is theswitching element in the intermediate stage that should be checked foravailable bandwidth, is set to one in step 915. Then, it is checked, instep 920, if i is less than or equal to the number of switching elementsin the intermediate stage. If i is not less than or equal to the numberof switching elements in the intermediate stage the channel cannot beestablished and the method is ended in step 910. If i is less than orequal to the number of switching elements in the intermediate stage, itis checked, in step 925, if there is any available bandwidth from theswitching element in the first stage where the input port of the channelis located to the switching element i in the intermediate stage. Ifthere is no available bandwidth, i is increased by one, in step 930, andthe method is continued in step 920 for the switching element i in theintermediate stage. If there is any available bandwidth, it is checked,in step 935, if there is any available bandwidth from the switchingelement i in the intermediate stage to the switching element in the laststage where the output port of the channel is located. If there is noavailable bandwidth, i is increased by one, in step 930, and the methodis continued in step 920 for the switching element i in the intermediatestage. If there is any available bandwidth, a bandwidth corresponding tothe least of the available bandwidth from the switching element in thefirst stage where the input port of the channel is located to theswitching element i in the intermediate stage, the available bandwidthfrom the switching element i in the intermediate stage to the switchingelement in the last stage where the output port of the channel islocated, and the remaining bandwidth to be allocated to the channel, isallocated to the channel in step 940. Then, in step 945, it is checkedif the total amount of bandwidth that has been allocated to the channelis equal to the bandwidth of the channel. If the total amount ofbandwidth that has been allocated to the channel is less than BW, i isincreased by one, in step 930, and the method is continued in step 920for this increased i. If the total amount of bandwidth that has beenallocated to the channel is equal to BW, the method is continued in step950 in which the switching element in the last stage where the outputport of the channel is located, each of the switching elements in theintermediate stage in which bandwidth has been allocated, and theswitching element in the first stage where the input port of the channelis located, are configured to map data pertaining to the multicastchannel into the available time slots. Finally, the method is ended instep 955.

[0088] The method described with reference to FIG. 4 may advantageouslybe combined with the method described with reference to FIG. 9. In thisway, according to the combined method, bandwidth may be allocated to themulticast channel along multiple paths from the input port of themulticast channel to one of the output ports of the multicast channel.This is advantageous since it will decrease the bandwidth usage betweenthe first and the intermediate stage in case of multicast.

[0089] In order to illustrate the method described with reference toFIG. 9, an example of the allocation of bandwidth to a multcast channelwill be described in the following with reference to FIG. 10A-D. FIG.10A-D schematically show different stages of the allocation of bandwidthto a channel in the multipath multistage switch in FIG. 8. Theallocation is done in accordance with the method described withreference to FIG. 9. The allocation is done using a control unit (notshown) which has a full view of the number of available time slotsthroughout the multipath multistage switch. The same numbering of theswitching elements and their respective input ports and output ports asin the description above with reference to FIG. 8, will be used.Furthermore, only the connections of interest are indicated in the FIGS.10A-D. For these connection, an indication of occupied time slots offrames in bitstreams on each connection of interest are indicated as anO in the corresponding time slot.

[0090] The establishment of a channel with a bandwidth corresponding tothree time slots out of four in each frame, from the second input portof the first switching element of the first stage to the third outputport of the first switching element in the last stage, is requested. Therequest is signalled to the control unit (not shown), which has a fullview of the number of available time slots throughout the multipathmultistage switch. When the method starts the remaining bandwidth to beallocated to the channel is bandwidth corresponding to three time slots.First, the available bandwidth in the third output port of the firstswitching element in the last stage is determined. In FIG. 10A it isshown that the there are three available time slots at the third outputport of the first switching element in the last stage. Thus, there isenough bandwidth. Then, the first switching element in the intermediatestage is chosen and the available bandwidth from the first switchingelement in the first stage to the first switching element in theintermediate is determined. In FIG. 10A it is shown that there are twotime slots available between these two switching elements. Then, theavailable bandwidth between the first switching element in theintermediate stage to the first switching element in the last stage isdetermined. In FIG. 10A it is shown that there is one time slotavailable between these two switching elements. Then, it is determinedwhich is the least of the bandwidth between the first switching elementin the first stage and the first switching element in the intermediatestage, the bandwidth between the first switching element in theintermediate stage and the first switching element in the last stage,and the remaining bandwidth to be allocated to the channel. In this casethe bandwidth corresponding to one time slot between the first switchingelement in the intermediate stage and the first switching element in thelast stage is the least. Thus, bandwidth corresponding to one time slotis allocated to the channel.

[0091] Since the bandwidth allocated to the channel is less than thetotal bandwidth of the channel, the second switching element in theintermediate stage is chosen and the available bandwidth from the firstswitching element in the first stage to the second switching element inthe intermediate is determined. In FIG. 10B it is shown that there isone time slots available between these two switching elements. Then, theavailable bandwidth between the second switching element in theintermediate stage to the first switching element in the last stage isdetermined. In FIG. 10B it is shown that there is no time slotsavailable between these two switching elements. Thus, no bandwidth canbe allocated to the channel.

[0092] Since the bandwidth allocated to the channel is still less thanthe total bandwidth of the channel, the third switching element in theintermediate stage is chosen and the available bandwidth from the firstswitching element in the first stage to the third switching element inthe intermediate is determined. In FIG. 10C it is shown that there aretwo time slots available between these two switching elements. Then, theavailable bandwidth between the third switching element in theintermediate stage to the first switching element in the last stage isdetermined. In FIG. 10C it is shown that there are two time slotsavailable between these two switching elements. Then, it is determinedwhich is the least of the bandwidth between the first switching elementin the first stage and the first switching element in the intermediatestage, the bandwidth between the first switching element in theintermediate stage and the first switching element in the last stage,and the remaining bandwidth to be allocated to the channel. In this casethey are all equal. Thus, bandwidth corresponding to two time slot areallocated to the channel.

[0093] Now, since the bandwidth allocated to the channel is equal to thebandwidth of the channel, each switching element through which thechannel is to be switched is configured so that data pertaining to themulticast channel are mapped into the available time slots in each ofthese switching elements. More specifically, the slot mapping table(SMT) of each of these switching elements is reconfigured using thecontrol unit (not shown) which has a full view of these SMT:s and thus,of which time slots are available. The reconfiguration is done first inswitching elements in the last stage, then in switching elements in theintermediate switch, and finally in switching elements in the firststage.

[0094] In FIG. 10D, the mapping of data L, M and N pertaining to thechannel into the available time slots, is shown.

[0095] Furthermore, in an alternative, both the embodiment describedwith reference to FIG. 1 and the embodiment described with reference toFIG. 6 may be realised such that the input stage and the output stageare implemented in the same physical equipment. In FIG. 11 such arealisation of a multipath multistage switch according to the invention,is shown. The multipath multistage switch comprises a common input andoutput stage 1105 and an intermediate stage 1110. As can be seen fromthe figure the switching elements 1115, 1120 and 1125 in the commoninput and output stage 1105 each has twice as many input ports andoutput ports as each switching element of the switching elements 1130,1135 and 1140 in the intermediate stage 1110. Moreover, this realisationhas the advantage that data that should be switched from an input portin a switching element in the common input and output stage 1105 to anoutput port in the same switching element may be switched internally inthe switching element. Thus, this type of data does not use anybandwidth in the intermediate stage.

[0096] In one example of a realisation in accordance with FIG. 11, eachof the switch elements 1115, 1120, 1125, 1130, 1135, 1140 is a separateswitch, which may be placed on different premises. In this type ofrealisation the set-up of channels and the time switching of each switchis preferably controlled by means of a distributed scheme, i.e. when achannel is to be set-up, the set-up is controlled locally at each switchbased on information in requirement messages and response messages. Forexample such a distributed scheme could use a signalling scheme thataccommodates for the fact that there are multiple paths from one switchto another switch and that uses load sharing between the paths by meansof Crank Back.

[0097] In another example of a realisation in accordance with FIG. 11,each of the switch elements 1115, 1120, 1125 are mounted on a respectiveboard, whilst the switch elements 1130, 1135, 1140 are mounted on thesame board. In this type of realisation the set-up of channels and thetime switching of each switch is preferably controlled by means of acentralised control unit as described above with reference to FIG. 1.

[0098] The embodiments of multipath multistage switches described withreference to FIG. 1 and FIG. 6, respectively, and the combinationthereof, may be used with advantage in several network scenarios,including both packet switched and circuit switched networks. Twoexample scenarios are shown in FIG. 12 and FIG. 13 and will be describedin the following.

[0099] In FIG. 12 a network in which the multipath multistage switch inFIG. 1 or FIG. 6, respectively, may be used with advantage, is shown. Inthis scenario the multipath multistage switch 1205 is a DTM (DynamicTransfer Mode) switch, which is used as a multiservice switch. The DTMswitch 1205 is connected to another DTM switch 1210 via a DTM interface.Furthermore, it is connected to a DWDM (Dense Wavelength DivisionMultiplexing) node 1215 via an optical interface. The DWDM node 1215 isconnected to another DWDM node 1220 via a DWDM interface on which eachDTM channel from the DTM switch 1205 are sent on a different wavelength.Moreover, the DTM switch 1205 is connected to a PSTN (Public SwitchedTelephone Network) node 1225 by means of PDH (Plesiochronous DigitalHierarchy) technology and an IP (Internet Protocol) router 1230.Finally, the DTM switch 1205 is connected to a bi-directional DTM ring1235 with three PDH nodes 1240, 1245 and 1250 connected to it.

[0100] In FIG. 13 a scenario where the multipath multistage switch inFIG. 1 or FIG. 6, respectively, or a combination thereof is applied inan IP router, is schematically shown. In this scenario the multipathmultistage switch 1305 is the switch fabric of the IP router. A numberof line cards 1315-1340 are connected to the switch 1305. The line cardscomprises IP interworking functionality and act as interfaces betweenthe IP network and the switch 1305. Furthermore, the underlying protocolthe IP traffic is transported over on the connections 1345-1370 maydiffer. For example, the link 1330 may be an Ethernet link, the link1335 may be an SONET link, the link 1340 may be a DWDM link, etc.

1. An apparatus for switching data between a first set of bitstreams anda second set of bitstreams, each of said bitstreams being divided intorecurring frames and each of said recurring frames being divided intotime slots, comprising: a first set of switching elements, at least oneintermediate set of switching elements, and a last set of switchingelements, wherein each switching element comprises a number of inputports and a number of output ports, and a control unit for controllingthe allocation of bandwidth in outgoing bitstreams, referring to theoutput ports of the switching elements, said control unit beingoperatively connected to each of the switching elements, wherein theinput ports of said first set of switching elements are arranged toreceive said first set of bitstreams and the output ports of eachswitching element in said first set of switching elements areoperatively connected to input ports of more than one switching elementin one of said at least one intermediate set of switching elements, andwherein the input ports of each switching element of said last set ofswitching elements are operatively connected to output ports of morethan one switching element in one of said at least one intermediate setof switching elements and the output ports of said last set of switchingelements are arranged to provide said second set of bitstreams, andwherein each switching element is arranged so that it provides for bothtime and space switching of data from incoming bitstreams, referring tothe input ports of the switching element, to outgoing bitstreams,referring to the output ports of the switching element.
 2. The apparatusaccording to claim 1, wherein said switching elements each comprise aslot mapping table designating, for each outgoing time slot of frames ofoutgoing bitstreams, referring to the output ports of the switchingelement, an incoming time slot of a frame of an incoming bitstream,referring to an input port of the switching element, from which incomingtime slot data that should be written into to the outgoing time slotshould be fetched, and wherein said control unit is arranged to controlthe behaviour of the slot mapping table of each switching element. 3.The apparatus according to claim 1, wherein said switching elements arearranged so that data which are received between a pair of consecutivestart of frame signals at input ports of switching elements in saidfirst set of switching elements, will be received between a pair ofconsecutive start of frame signals at input ports of switching elementsin said last set of switching elements.
 4. The apparatus according toclaim 1, wherein said switching elements are arranged so that allbitstreams between output ports of switching elements and input ports ofother switching elements are asynchronous on a bit level, whilst theyare synchronous on a frame level.
 5. A method for allocating bandwidthto a multicast channel from an input port to at least two output portsin a switching apparatus comprising a first set of switching elements,an intermediate set of switching elements, and a last set of switchingelements, wherein each switching element comprises a number of inputports and a number of output ports, and wherein the output ports of saidfirst set of switching elements are operatively connected to the inputports of said intermediate set of switching elements, and wherein theoutput ports of said intermediate set of switching elements areoperatively connected to the input ports of said last set of switchingelements, comprising the steps of: a) determining whether there is oneswitching element in said intermediate set of switching elements, forwhich there is enough available bandwidth to carry the channel in abitstream from the switching element of said first set of switchingelements comprising said input port to said one switching element, andfor which there is enough available bandwidth to carry the channel inbitstreams from said one switching element to the switching elements insaid last set of switching elements comprising said at least two outputports; and b) allocating, if it is determined that there is one suchswitching element in said intermediate set of switching elements,bandwidth to the channel in said bitstream from the switching element ofsaid first set of switching elements comprising said input port to saidone switching element, and in said bitstreams from said one switchingelement to the switching elements in said last set of switching elementscomprising said at least two output ports.
 6. The method according toclaim 5, wherein step a) comprises the steps of: a1) determining whetherthere is one switching element in said intermediate set of switchingelements, for which there is enough available bandwidth to carry thechannel in bitstreams from said one switching element to the switchingelements in said last set of switching elements comprising said at leasttwo output ports; and a2) determining, in the case where there is onesuch switching element, whether there is enough available bandwidth tocarry the channel in one bitstream from the switching element of saidfirst set of switching elements comprising said input port to said oneswitching element.
 7. The method according to claim 5 or 6, furthercomprising the steps of: c) determining, if there is not one suchswitching element in said intermediate set of switching elements,whether there are two switching elements in said intermediate set ofswitching elements, for which there is enough available bandwidth tocarry the channel in bitstreams from the switching element of said firstset of switching elements comprising said input port to said twoswitching element, and there is enough available bandwidth to carry thechannel in bitstreams from said two switching elements to the switchingelements in said last set of switching elements comprising said at leasttwo output ports; and d) allocating, if there are two such switchingelements in said intermediate set of switching elements, bandwidth tothe channel in said bitstreams from the switching element of said firstset of switching elements comprising said input port to said twoswitching elements, and in said bitstreams from said two switchingelements to the switching elements in said last set of switchingelements comprising said at least two output ports.